Análise e síntese de um algoritmo “Phase-Locked Loop” robusto para estimação de amplitude, fase e freqüência de sinais elétricos

Abstract

The always more restrictive energy quality benchmarks, pushed on by consumers, associated with the electric sector deregulamentation has been imposing the necessity, for the concessionaries, of a better and decentralized monitoring of energy electric quality. At the same time, the increase of nonlinear loads connected to the electric network, among other facts, has been increasing the complexities associated with this electric signals parameters estimation. So, the synthesis of efficient parameters estimation algorithms, with low computational effort and with easy implementation on low-cost hardware systems has becoming a priority for the energy quality area. Based on these assumptions, this work deals with the design and synthesis of a robust Phase-Locked-Loop (PLL) structure, more specifically an Enhanced Quadrature Phase-Locked-Loop (ER-QPLL) with capacity of estimate several parameters, more specifically phase, frequency and amplitude, from any input signal. The synthesis of this ER-QPLL structure was based on the enhancement of a Quadrature Phase-Locked-Loop (QPLL) that can estimate the parameters of the fundamental component of any input signal thought the information acquired with the acquisition of its phase and quadrature components. The enhancements of this QPLL structure were, basically, the introduction of a adaptive notch filter on its input, associated with an delta operator (δ), a tool of the gamma transformer (γ), for modeling the whole structure. A significant improvement in the SNR of the input signal, without degradation of the dynamic structure output, was achieved with the introduction of the notch filter. The adaptive characteristics of this notch filter can deal, in a very good way, with the non-stationery properties of the input signals. The structure implementation based on delta operator (δ) can assure an almost ideal performance for limited precision systems of, at least, 16 bits. According to the results obtained in this work, the performance of the proposed structure can be considered very good, even when dealing with high sampling rates relative to the network frequency operation. Finally, a structure based on a microprocessor DSP from TMS320 family was proposed and implemented showing its feasibility for fixed-point hardware.